894 search results - page 40 / 179 » Optimizations for LTL Synthesis |
89
Voted
ICCAD
2009
IEEE
14 years 8 months ago
2009
IEEE
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially i...
ICCAD
2007
IEEE
15 years 5 months ago
2007
IEEE
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
FCCM
2002
IEEE
15 years 4 months ago
2002
IEEE
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
CCE
2004
14 years 11 months ago
2004
: This paper describes the implementation of a meta-heuristic optimization approach, Tabu Search (TS), for Heat Exchanger Networks (HEN) synthesis and compares this approach to oth...