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» Optimizations for LTL Synthesis
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ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
15 years 9 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid
86
Voted
DSD
2007
IEEE
87views Hardware» more  DSD 2007»
15 years 7 months ago
On the Construction of Small Fully Testable Circuits with Low Depth
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
Görschwin Fey, Anna Bernasconi, Valentina Cir...
164
Voted
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
15 years 6 months ago
Droplet routing in the synthesis of digital microfluidic biochips
same level of system-level CAD support that is now commonplace in the IC industry.Recent advances in microfluidics are expected to lead to sensor systems for high-throughput bioche...
Fei Su, William L. Hwang, Krishnendu Chakrabarty
114
Voted
EUROGP
2006
Springer
135views Optimization» more  EUROGP 2006»
15 years 4 months ago
Dynamic Scheduling with Genetic Programming
This paper investigates the use of genetic programming in automatized synthesis of scheduling heuristics. The applied scheduling technique is priority scheduling, where the next st...
Domagoj Jakobovic, Leo Budin
90
Voted
DAC
2002
ACM
16 years 1 months ago
Efficient code synthesis from extended dataflow graphs for multimedia applications
This paper presents efficient automatic code synthesis techniques from dataflow graphs for multimedia applications. Since multimedia applications require large size buffers contai...
Hyunok Oh, Soonhoi Ha