Abstract. Synthesis is the automatic construction of a system from its specification. In the classical synthesis algorithms it is always assumed the system is “constructed from ...
Abstract. We consider the control problem for timed automata against specifications given as MTL formulas. The logic MTL is a linear-time timed temporal logic which extends LTL wit...
Patricia Bouyer, Laura Bozzelli, Fabrice Chevalier
This paper upgrades Regular Linear Temporal Logic (RLTL) with past operators and complementation. RLTL is a temporal logic that extends the expressive power of linear temporal logi...
Abstract-- We present a computational framework for automatic synthesis of a feedback control strategy for a piecewise affine (PWA) system from a specification given as a Linear Te...
Jana Tumova, Boyan Yordanov, Calin Belta, Ivana Ce...
This paper present a novel interface synthesis approach based on a one-sided interface description. Whereas most other approaches consider interface synthesis as optimizing a chan...