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» Optimizations for LTL Synthesis
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ISSS
1997
IEEE
103views Hardware» more  ISSS 1997»
15 years 4 months ago
A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
Chih-Tung Chen, Kayhan Küçük&cced...
69
Voted
ICCAD
1996
IEEE
119views Hardware» more  ICCAD 1996»
15 years 4 months ago
An algorithm for synthesis of system-level interface circuits
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with ...
Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
94
Voted
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
15 years 4 months ago
Synthesis of Self-Testable Controllers
The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test reg...
Sybille Hellebrand, Hans-Joachim Wunderlich
100
Voted
ASPDAC
1995
ACM
127views Hardware» more  ASPDAC 1995»
15 years 4 months ago
Reclocking for high-level synthesis
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran
86
Voted
AUTOMATICA
2008
114views more  AUTOMATICA 2008»
15 years 23 days ago
A synthesis approach for output feedback robust constrained model predictive control
This paper addresses the synthesis approach to output feedback robust model predictive control for systems with polytopic description, bounded state disturbance and measurement no...
BaoCang Ding, YuGeng Xi, Marcin T. Cychowski, Thom...