894 search results - page 76 / 179 » Optimizations for LTL Synthesis |
111
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ASPDAC
2009
ACM
15 years 7 months ago
2009
ACM
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, wo...
98
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ASPDAC
2009
ACM
15 years 7 months ago
2009
ACM
—Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced...
111
Voted
GLVLSI
2005
IEEE
15 years 6 months ago
2005
IEEE
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
LCPC
2001
Springer
15 years 5 months ago
2001
Springer
Abstract. The DEFACTO project - a Design Environment For Adaptive Computing TechnOlogy - is a system that maps computations, expressed in high-level languages such as C, directly o...
129
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DATE
2000
IEEE
15 years 5 months ago
2000
IEEE
Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algor...