894 search results - page 82 / 179 » Optimizations for LTL Synthesis |
114
Voted
DAC
2005
ACM
16 years 1 months ago
2005
ACM
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
97
Voted
DAC
2006
ACM
16 years 1 months ago
2006
ACM
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
110
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VLSID
2007
IEEE
16 years 1 months ago
2007
IEEE
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...
101
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CEC
2008
IEEE
15 years 7 months ago
2008
IEEE
— The high-level synthesis process involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the ...
ISQED
2007
IEEE
15 years 7 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...