894 search results - page 83 / 179 » Optimizations for LTL Synthesis |
95
Voted
IESS
2007
Springer
15 years 6 months ago
2007
Springer
: Much effort in RTL design has been devoted to developing “push-button” types of tools. However, given the highly complex nature, and lack of control on RTL design, push-butt...
112
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CODES
2006
IEEE
15 years 6 months ago
2006
IEEE
In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylization...
128
Voted
SCOPES
2004
Springer
15 years 6 months ago
2004
Springer
Abstract. Synthesis of digital signal processing (DSP) software from dataflow-based formal models is an effective approach for tackling the complexity of modern DSP applications. I...
111
Voted
ISPD
1999
ACM
15 years 5 months ago
1999
ACM
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
113
Voted
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...