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» Optimizations for LTL Synthesis
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92
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ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
15 years 6 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
ISCAS
2002
IEEE
125views Hardware» more  ISCAS 2002»
15 years 5 months ago
Switching activity estimation of finite state machines for low power synthesis
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
87
Voted
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
15 years 4 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
92
Voted
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
15 years 4 months ago
A general state graph transformation framework for asynchronous synthesis
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
Bill Lin, Chantal Ykman-Couvreur, Peter Vanbekberg...
SIGGRAPH
1990
ACM
15 years 4 months ago
Reusable motion synthesis using state-space controllers
The use of physically-based techniques for computer animation can result in realistic object motion. The price paid for physically-based motion synthesis lies in increased computa...
Michiel van de Panne, Eugene Fiume, Zvonko G. Vran...