52 search results - page 3 / 11 » Optimized Timed Hardware Software Cosimulation without Roll-... |
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
Abstract—This paper addresses the problem of execution time estimation for tasks in a software pipeline independent of the application structure or the underlying architecture. A...
CGO
2004
IEEE
13 years 10 months ago
2004
IEEE
We study several major characteristics of dynamic optimization within the PARROT power-aware, trace-cachebased microarchitectural framework. We investigate the benefit of providin...
VTS
1997
IEEE
13 years 10 months ago
1997
IEEE
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
ISQED
2002
IEEE
13 years 11 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
EMSOFT
2004
Springer
13 years 11 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...