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ICCD
2001
IEEE
90views Hardware» more  ICCD 2001»
16 years 3 months ago
Interconnect-centric Array Architectures for Minimum SRAM Access Time
‡ Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are r...
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, Jame...
WG
2007
Springer
16 years 13 days ago
The Complexity of Bottleneck Labeled Graph Problems
Abstract. We present hardness results, approximation heuristics, and exact algorithms for bottleneck labeled optimization problems arising in the context of graph theory. This long...
Refael Hassin, Jérôme Monnot, Danny S...
143
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DATE
2004
IEEE
110views Hardware» more  DATE 2004»
15 years 10 months ago
Interactive Cosimulation with Partial Evaluation
We present a technique to improve the efficiency of hardware-software cosimulation, using design information known at simulator compile-time. The generic term for such optimizatio...
Patrick Schaumont, Ingrid Verbauwhede
JSS
2008
65views more  JSS 2008»
15 years 6 months ago
Process pipeline scheduling
This paper explores how process pipeline scheduling may become a viable strategy for executing workflows. It first details a workflow optimization and execution algorithm that redu...
Melissa Lemos, Marco A. Casanova, Antonio L. Furta...
PE
2007
Springer
104views Optimization» more  PE 2007»
15 years 5 months ago
Flow vs. time sampling for throughput performance evaluation
We introduce two throughput metrics referred to as flow- and time-sampled throughputs. The former gives the throughput statistics of an arbitrary flow while the latter weights t...
T. Bonald, M.-A. Tran