‡ Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are r...
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, Jame...
Abstract. We present hardness results, approximation heuristics, and exact algorithms for bottleneck labeled optimization problems arising in the context of graph theory. This long...
We present a technique to improve the efficiency of hardware-software cosimulation, using design information known at simulator compile-time. The generic term for such optimizatio...
This paper explores how process pipeline scheduling may become a viable strategy for executing workflows. It first details a workflow optimization and execution algorithm that redu...
Melissa Lemos, Marco A. Casanova, Antonio L. Furta...
We introduce two throughput metrics referred to as flow- and time-sampled throughputs. The former gives the throughput statistics of an arbitrary flow while the latter weights t...