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» Optimizing Graph Algorithms for Improved Cache Performance
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186
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ICCD
2011
IEEE
296views Hardware» more  ICCD 2011»
14 years 2 months ago
DPPC: Dynamic power partitioning and capping in chip multiprocessors
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
Kai Ma, Xiaorui Wang, Yefu Wang
124
Voted
CF
2010
ACM
15 years 2 months ago
Efficient cache design for solid-state drives
Solid-State Drives (SSDs) are data storage devices that use solid-state memory to store persistent data. Flash memory is the de facto nonvolatile technology used in most SSDs. It ...
Miaoqing Huang, Olivier Serres, Vikram K. Narayana...
134
Voted
TOG
2008
137views more  TOG 2008»
15 years 2 months ago
Efficient traversal of mesh edges using adjacency primitives
Processing of mesh edges lies at the core of many advanced realtime rendering techniques, ranging from shadow and silhouette computations, to motion blur and fur rendering. We pre...
Pedro V. Sander, Diego Nehab, Eden Chlamtac, Hugue...
124
Voted
IDEAS
2006
IEEE
82views Database» more  IDEAS 2006»
15 years 8 months ago
A similarity based approach for integrated Web caching and content replication in CDNs
Web caching and content replication techniques emerged to solve performance problems related to the Web. We propose a generic non-parametric heuristic method that integrates both ...
Konstantinos Stamos, George Pallis, Charilaos Thom...
130
Voted
HPCA
1999
IEEE
15 years 7 months ago
Impulse: Building a Smarter Memory Controller
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Ma...