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» Optimizing Graph Algorithms for Improved Cache Performance
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135
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CEC
2010
IEEE
15 years 3 months ago
Functionalization of microarray devices: Process optimization using a multiobjective PSO and multiresponse MARS modeling
An evolutionary approach for the optimization of microarray coatings produced via sol-gel chemistry is presented. The aim of the methodology is to face the challenging aspects of t...
Laura Villanova, Paolo Falcaro, Davide Carta, Iren...
90
Voted
DAC
2005
ACM
16 years 3 months ago
MiniBit: bit-width optimization via affine arithmetic
MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the intege...
Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayn...
114
Voted
ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
15 years 11 months ago
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning
This paper proposes a new formalism for layout-driven optimization of datapaths. It is based on preserving an arithmetic bit level representation of the arithmetic circuit portion...
Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Mi...
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
15 years 9 months ago
Area optimization of multi-cycle operators in high-level synthesis
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
María C. Molina, Rafael Ruiz-Sautua, Jose M...
SIGMETRICS
2010
ACM
178views Hardware» more  SIGMETRICS 2010»
15 years 7 months ago
Optimality, fairness, and robustness in speed scaling designs
System design must strike a balance between energy and performance by carefully selecting the speed at which the system will run. In this work, we examine fundamental tradeoffs i...
Lachlan L. H. Andrew, Minghong Lin, Adam Wierman