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» Optimizing Graph Algorithms for Improved Cache Performance
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PCI
2005
Springer
15 years 7 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
HPCA
2007
IEEE
15 years 8 months ago
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
Shared memory multiprocessors play an increasingly important role in enterprise and scientific computing facilities. Remote misses limit the performance of shared memory applicat...
Liqun Cheng, John B. Carter, Donglai Dai
ADBIS
1998
Springer
100views Database» more  ADBIS 1998»
15 years 6 months ago
Multiple Range Query Optimization in Spatial Databases
In order to answer efficiently range queries in 2-d R-trees, first we sort queries by means of a space filling curve, then we group them together, and finally pass them for process...
Apostolos Papadopoulos, Yannis Manolopoulos
91
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GECCO
2004
Springer
15 years 7 months ago
A Caching Genetic Algorithm for Spectral Breakpoint Matching
Abstract. Two methods were evaluated for performing spectral breakpoint matching: a multi-level pruned exhaustive search and a genetic algorithm. The GA found matches about as good...
Jonathan Mohr, Xiaobo Li
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
15 years 5 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...