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EUROMICRO
1998
IEEE
15 years 6 months ago
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems
The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have develop...
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...
CORR
2007
Springer
93views Education» more  CORR 2007»
15 years 2 months ago
Dualheap Sort Algorithm: An Inherently Parallel Generalization of Heapsort
A generalization of the heapsort algorithm is proposed. At the expense of about 50% more comparison and move operations for typical cases, the dualheap sort algorithm offers sever...
Greg Sepesi
120
Voted
CAINE
2004
15 years 3 months ago
Adjusting Web Caching Computers to Reduce Communication Channel Allocation
On the Internet, it is common practice to use a computer to provide web caching services. Such services aim to reduce network utilization and improve access time to a web page. Li...
R. Zuck, A. Williams, B. Kair, H. Bui, Catherine S...
IPPS
2000
IEEE
15 years 6 months ago
Dynamic Data Layouts for Cache-Conscious Factorization of DFT
Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimizationtechniques for computing ...
Neungsoo Park, Dongsoo Kang, Kiran Bondalapati, Vi...
IPPS
2005
IEEE
15 years 8 months ago
An Experimental Study of Parallel Biconnected Components Algorithms on Symmetric Multiprocessors (SMPs)
We present an experimental study of parallel biconnected components algorithms employing several fundamental parallel primitives, e.g., prefix sum, list ranking, sorting, connect...
Guojing Cong, David A. Bader