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INFOCOM
2010
IEEE
15 years 1 months ago
Analyzing the Performance of Greedy Maximal Scheduling via Local Pooling and Graph Theory
—Efficient operation of wireless networks and switches requires using simple (and in some cases distributed) scheduling algorithms. In general, simple greedy algorithms (known a...
Berk Birand, Maria Chudnovsky, Bernard Ries, Paul ...
124
Voted
AAAI
2006
15 years 4 months ago
Memory Intensive Branch-and-Bound Search for Graphical Models
AND/OR search spaces have recently been introduced as a unifying paradigm for advanced algorithmic schemes for graphical models. The main virtue of this representation is its sens...
Radu Marinescu 0002, Rina Dechter
EURODAC
1995
IEEE
112views VHDL» more  EURODAC 1995»
15 years 6 months ago
Post routing performance optimization via tapered link insertion and wiresizing
Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can re...
Tianxiong Xue, Ernest S. Kuh
131
Voted
CGF
2006
136views more  CGF 2006»
15 years 2 months ago
Cache-Efficient Layouts of Bounding Volume Hierarchies
We present a novel algorithm to compute cache-efficient layouts of bounding volume hierarchies (BVHs) of polygonal models. Our approach does not make any assumptions about the cac...
Sung-Eui Yoon, Dinesh Manocha
103
Voted
ISVLSI
2003
IEEE
97views VLSI» more  ISVLSI 2003»
15 years 8 months ago
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
Andrew B. Kahng, Bao Liu