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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 3 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ATMN
1996
14 years 11 months ago
Dynamic time sharing: a new approach for congestion management
A new approach for bandwidth allocation and congestion control is reported in this paper, which is of the Rate Controlled admission with Priority Scheduling service type. It is ca...
Adrian Popescu, Parag Pruthi
BTW
2003
Springer
109views Database» more  BTW 2003»
15 years 3 months ago
Transbase: a Leading-edge ROLAP Engine Supporting Multidimensional Indexing and Hierarchy Clustering
: Analysis-oriented database applications, such as data warehousing or customer relationship management, play a crucial role in the database area. In general, the multidimensional ...
Roland Pieringer, Klaus Elhardt, Frank Ramsak, Vol...
DAC
2000
ACM
15 years 11 months ago
Memory aware compilation through accurate timing extraction
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau
CPAIOR
2007
Springer
15 years 4 months ago
A Global Constraint for Total Weighted Completion Time
We introduce a novel global constraint for the total weighted completion time of activities on a single unary capacity resource. For propagating the constraint, an O(n4 ) algorithm...
András Kovács, J. Christopher Beck