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VLSID
2010
IEEE
170views VLSI» more  VLSID 2010»
14 years 3 months ago
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Contro
The continuous increase of leakage power consumption in deep sub-micro technologies necessitates more aggressive leakage control. Runtime leakage control (RTLC) is effective, si...
Hao Xu, Wen-Ben Jone, Ranga Vemuri
MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
15 years 2 months ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...
EURONGI
2005
Springer
15 years 3 months ago
Service Level Agreement Enforcement for Differentiated Services
This paper describes a hierarchical architecture of active policies that performs the management of a differentiated services (DiffServ) network. These policies monitor quality of ...
Paulo Rogério Pereira
APLAS
2008
ACM
15 years 7 hour ago
Certified Reasoning in Memory Hierarchies
Abstract. Parallel programming is rapidly gaining importance as a vector to develop high performance applications that exploit the improved capabilities of modern computer architec...
Gilles Barthe, César Kunz, Jorge Luis Sacch...
EUROPAR
2010
Springer
14 years 10 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...