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» Optimizing Logic Design Using Boolean Transforms
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PATMOS
2005
Springer
15 years 3 months ago
Power - Performance Optimization for Custom Digital Circuits
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
Radu Zlatanovici, Borivoje Nikolic
ISQED
2007
IEEE
146views Hardware» more  ISQED 2007»
15 years 4 months ago
Parameter-Variation-Aware Analysis for Noise Robustness
This paper studies the impact of variability on the noise robustness of logic gates using noise rejection curves (NRCs). NRCs allow noise pulses to be modeled using magnitude-dura...
Mosin Mondal, Kartik Mohanram, Yehia Massoud
DATE
2006
IEEE
124views Hardware» more  DATE 2006»
15 years 3 months ago
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
GECCO
2006
Springer
133views Optimization» more  GECCO 2006»
15 years 1 months ago
Evolutionary search for optimal combinations of markers in clothing manufacturing
Optimizing combinations of placements of parts, known as markers, is an important preparatory step in order-based industrial production of clothes. Given a work order in the form ...
Bogdan Filipic, Iztok Fister, Marjan Mernik
HASE
1998
IEEE
15 years 2 months ago
Analytical Partition of Software Components for Evolvable and Reliable MEMS Design Tools
Transforming software requirements into a software design involves the iterative partition of a solution into software components. The process is human-intensive and does not guar...
Carol L. Hoover, Pradeep K. Khosla