868 search results - page 112 / 174 » Optimizing Logic Design Using Boolean Transforms |
75
Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...
FPGA
2006
ACM
15 years 1 months ago
2006
ACM
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
ICCS
2001
Springer
15 years 2 months ago
2001
Springer
Abstract. Sparse matrix-vector multiplication is an important computational kernel that tends to perform poorly on modern processors, largely because of its high ratio of memory op...
ICRA
2007
IEEE
15 years 4 months ago
2007
IEEE
Abstract— We study the problem of designing control strategies for nondeterministic transitions systems enforcing the satisfaction of Linear Temporal Logic (LTL) formulas over th...
IBIS
2006
14 years 9 months ago
2006
: Schema matching is the task of finding semantic correspondences between elements of two schemas, which plays a key role in many database applications. In this paper, we cast the ...