868 search results - page 120 / 174 » Optimizing Logic Design Using Boolean Transforms |
84
Voted
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...
RSP
2003
IEEE
15 years 2 months ago
2003
IEEE
The paper shows the outlines of the SLAM system and how its design is suitable for automating rapid prototyping. The system includes a very expressive object oriented specificati...
ASAP
2004
IEEE
15 years 1 months ago
2004
IEEE
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...
ASAP
2005
IEEE
15 years 3 months ago
2005
IEEE
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
ICC
1997
IEEE
15 years 1 months ago
1997
IEEE
— This letter considers a combined source-channel coding scheme for image transmission over the uplink of a wireless IS-95 code division multiple access (CDMA) channel using disc...