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» Optimizing Logic Design Using Boolean Transforms
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DAC
2002
ACM
15 years 10 months ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid
ICS
2009
Tsinghua U.
15 years 4 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
KESAMSTA
2007
Springer
15 years 3 months ago
Quantitative Analysis of Single-Level Single-Mediator Multi-agent Systems
Queueing Theory deals with problems where some restricted resource should be shared between competitive flow of requests. In this paper we use Queueing Theory methods to perform a...
Moon Ho Lee, Aliaksandr Birukou, Alexander N. Dudi...
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
15 years 3 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
15 years 1 months ago
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
Jordi Cortadella, Michael Kishinevsky, Steven M. B...