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» Optimizing Logic Design Using Boolean Transforms
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VEE
2010
ACM
218views Virtualization» more  VEE 2010»
15 years 4 months ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...
DAC
2002
ACM
15 years 10 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
92
Voted
JFP
2000
163views more  JFP 2000»
14 years 9 months ago
Automatic useless-code elimination for HOT functional programs
In this paper we present two type inference systems for detecting useless-code in higher-order typed functional programs. Type inference can be performed in an efficient and compl...
Ferruccio Damiani, Paola Giannini
ISCA
2003
IEEE
144views Hardware» more  ISCA 2003»
15 years 2 months ago
Half-Price Architecture
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
Ilhyun Kim, Mikko H. Lipasti
66
Voted
DSD
2004
IEEE
104views Hardware» more  DSD 2004»
15 years 1 months ago
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...