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» Optimizing Logic Design Using Boolean Transforms
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DAC
2005
ACM
15 years 10 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
SIGMOD
2005
ACM
145views Database» more  SIGMOD 2005»
15 years 9 months ago
Stratified Computation of Skylines with Partially-Ordered Domains
In this paper, we study the evaluation of skyline queries with partially-ordered attributes. Because such attributes lack a total ordering, traditional index-based evaluation algo...
Chee Yong Chan, Pin-Kwang Eng, Kian-Lee Tan
CLOUD
2010
ACM
15 years 2 months ago
Nephele/PACTs: a programming model and execution framework for web-scale analytical processing
We present a parallel data processor centered around a programming model of so called Parallelization Contracts (PACTs) and the scalable parallel execution engine Nephele [18]. Th...
Dominic Battré, Stephan Ewen, Fabian Hueske...
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 2 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
ESOP
1999
Springer
15 years 1 months ago
Dynamic Programming via Static Incrementalization
Abstract. Dynamicprogramming is an importantalgorithm design technique. It is used for solving problems whose solutions involve recursively solving subproblems that share subsubpro...
Yanhong A. Liu, Scott D. Stoller