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» Optimizing Logic Design Using Boolean Transforms
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VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
15 years 10 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler
FM
1999
Springer
121views Formal Methods» more  FM 1999»
15 years 1 months ago
Incremental Design of a Power Transformer Station Controller Using a Controller Synthesis Methodology
ÐIn this paper, we describe the incremental specification of a power transformer station controller using a controller synthesis methodology. We specify the main requirements as s...
Hervé Marchand, Mazen Samaan
ICCAD
2007
IEEE
115views Hardware» more  ICCAD 2007»
15 years 6 months ago
Timing optimization by restructuring long combinatorial paths
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...
Jürgen Werber, Dieter Rautenbach, Christian S...
ILP
2003
Springer
15 years 2 months ago
Query Optimization in Inductive Logic Programming by Reordering Literals
Query optimization is used frequently in relational database management systems. Most existing techniques are based on reordering the relational operators, where the most selective...
Jan Struyf, Hendrik Blockeel
DAC
2001
ACM
15 years 10 months ago
Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation
In this paper, we present a new technique for the e cient dynamic detection and removal of inactive clauses, i.e. clauses that do not a ect the solutions of interest of a Boolean ...
Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav A...