868 search results - page 21 / 174 » Optimizing Logic Design Using Boolean Transforms |
DAC
2004
ACM
15 years 1 months ago
2004
ACM
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
ICIP
2008
IEEE
15 years 11 months ago
2008
IEEE
We propose a block-based transform optimization and associated image compression technique that exploits regularity along directional image singularities. Unlike established work,...
FPGA
2008
ACM
14 years 11 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
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FMCAD
2009
Springer
15 years 4 months ago
2009
Springer
— There is a long history of investigations and debates on whether a sequence of retiming and resynthesis is complete for all sequential transformations (on steady states). It ha...
IS
2002
14 years 9 months ago
2002
In this paper, we explore the possibility of transforming queries with minimum and maximum predicates into equivalent queries that can be computed more efficiently. The main contr...