868 search results - page 26 / 174 » Optimizing Logic Design Using Boolean Transforms |
DAC
2006
ACM
15 years 10 months ago
2006
ACM
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
165
Voted
POPL
2008
ACM
15 years 10 months ago
2008
ACM
Translation validation consists of transforming a program and a posteriori validating it in order to detect a modification of its semantics. This approach can be used in a verifie...
76
Voted
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
86
Voted
FPGA
2004
ACM
15 years 1 months ago
2004
ACM
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
CHARME
2003
Springer
15 years 2 months ago
2003
Springer
We present a non-operational approach to specifying and analyzing shared memory consistency models. The method uses higher order logic to capture a complete set of ordering constra...