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» Optimizing Logic Design Using Boolean Transforms
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CAV
2010
Springer
286views Hardware» more  CAV 2010»
14 years 9 months ago
ABC: An Academic Industrial-Strength Verification Tool
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
Robert K. Brayton, Alan Mishchenko
SCAM
2003
IEEE
15 years 2 months ago
Unique Renaming of Java Using Source Transformation
This paper presents a flexible way in which a deisgn model extracted from Java programs can remain unified with the source code. Each entity declaration and reference in the Java ...
Xinping Guo, James R. Cordy, Thomas R. Dean
DATE
2008
IEEE
142views Hardware» more  DATE 2008»
14 years 11 months ago
Algorithms for Maximum Satisfiability using Unsatisfiable Cores
Many decision and optimization problems in Electronic Design Automation (EDA) can be solved with Boolean Satisfiability (SAT). Moreover, well-known extensions of SAT also find app...
João Marques-Silva, Jordi Planes
LISA
2004
14 years 11 months ago
Auto-configuration by File Construction: Configuration Management with newfig
A tool is described that provides for the automatic configuration of systems from a single description. The tool, newfig, uses two simple concepts to provide its functionality: bo...
William LeFebvre, David Snyder
DAC
2001
ACM
15 years 10 months ago
Transformations for the Synthesis and Optimization of Asynchronous Distributed Control
Asynchronous design has been the focus of renewed interest. However, a key bottleneck is the lack of high-quality CAD tools for the synthesis of large-scale systems which also all...
Michael Theobald, Steven M. Nowick