868 search results - page 36 / 174 » Optimizing Logic Design Using Boolean Transforms |
ICASSP
2008
IEEE
15 years 4 months ago
2008
IEEE
A new design approach for an allpass transformed analysis-synthesis filter-bank (AS FB) with subsampling is proposed, which can be used for adaptive subband processing with non-u...
89
Voted
GLVLSI
2008
IEEE
15 years 4 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
82
Voted
GECCO
2005
Springer
15 years 3 months ago
2005
Springer
This paper proposes and analyses the performance of a Genetic Algorithm (GA) using two new concepts, namely a static fitness function including a discontinuity measure and a fract...
CODES
2009
IEEE
14 years 10 months ago
2009
IEEE
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...
68
Voted
DAC
1994
ACM
15 years 1 months ago
1994
ACM
This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in a computation in such a way that a specific goal is ...