868 search results - page 58 / 174 » Optimizing Logic Design Using Boolean Transforms |
87
Voted
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
104
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
In this paper, we propose an exact algorithm for the problem of area optimization under a delay constraint in the synthesis of multiplierless FIR filters. To the best of our knowl...
110
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VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
128
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CC
2010
Springer
14 years 8 months ago
2010
Springer
Abstract. We prove lower bounds on the randomized two-party communication complexity of functions that arise from read-once boolean formulae. A read-once boolean formula is a formu...
IJCIM
2007
14 years 9 months ago
2007
Worldwide competition originated the development of Integrated E-Supply Chains (IESC) that are distributed manufacturing systems integrating international logistics and informatio...