868 search results - page 62 / 174 » Optimizing Logic Design Using Boolean Transforms |
FPL
2003
Springer
15 years 2 months ago
2003
Springer
By adapting to computations that are not so well supported by general-purpose processors, reconfigurable systems achieve significant increases in performance. Such computational sy...
FPL
1997
Springer
15 years 1 months ago
1997
Springer
Technology mapping can be viewed as the optimization problem of finding a minimum cost cover of the given Boolean network by choosing from given library of logic cells. The core of...
123
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SAS
2010
Springer
14 years 8 months ago
2010
Springer
Recent innovations in automatic parallelizing compilers are showing impressive speedups on multicore processors using shared memory with asynchronous channels. We have formulated a...
102
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GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
113
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FPGA
2001
ACM
15 years 2 months ago
2001
ACM
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...