Sciweavers

868 search results - page 91 / 174
» Optimizing Logic Design Using Boolean Transforms
Sort
View
CSFW
1999
IEEE
15 years 8 months ago
A Meta-Notation for Protocol Analysis
Most formal approaches to security protocol analysis are based on a set of assumptions commonly referred to as the "Dolev-Yao model." In this paper, we use a multiset re...
Iliano Cervesato, Nancy A. Durgin, Patrick Lincoln...
CASES
2003
ACM
15 years 9 months ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid
FMSP
2000
ACM
177views Formal Methods» more  FMSP 2000»
15 years 8 months ago
DSD: A schema language for XML
XML (eXtensible Markup Language) is a linear syntax for trees, which has gathered a remarkable amount of interest in industry. The acceptance of XML opens new venues for the appli...
Nils Klarlund, Anders Møller, Michael I. Sc...
TPHOL
2007
IEEE
15 years 10 months ago
Separation Logic for Small-Step cminor
Cminor is a mid-level imperative programming language; there are proved-correct optimizing compilers from C to Cminor and from Cminor to machine language. We have redesigned Cminor...
Andrew W. Appel, Sandrine Blazy
ARVLSI
2001
IEEE
289views VLSI» more  ARVLSI 2001»
15 years 8 months ago
A High-Performance 64-bit Adder Implemented in Output Prediction Logic
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
Sheng Sun, Larry McMurchie, Carl Sechen