868 search results - page 93 / 174 » Optimizing Logic Design Using Boolean Transforms |
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
DAC
2012
ACM
13 years 5 days ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
— With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally ef...
FPL
2006
Springer
15 years 1 months ago
2006
Springer
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorpl...
PDP
2005
IEEE
15 years 3 months ago
2005
IEEE
In this work we evaluate the implementation of a video encoder based on the 3D Wavelet Transform optimized for HyperThreading technology and SMPs. We design several implementation...