244 search results - page 5 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
86
Voted
CASES
2001
ACM
15 years 3 months ago
2001
ACM
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...
90
Voted
ICCD
1999
IEEE
15 years 4 months ago
1999
IEEE
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
117
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LCTRTS
2005
Springer
15 years 5 months ago
2005
Springer
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
115
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IEEEPACT
2005
IEEE
15 years 5 months ago
2005
IEEE
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
114
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ISCAPDCS
2003
15 years 1 months ago
2003
In modern computer systems loops present a great deal of opportunities for increasing Instruction Level and Thread Level Parallelism. Loop unrolling is a technique used to obtain ...