12 search results - page 1 / 3 » Optimizing Reaching Definitions Overhead in Queue Processors |
64
Voted
JCIT
2007
14 years 9 months ago
2007
Queue computers are a viable option for embedded systems design. Queue computers feature a dense instruction set, high parallelism, low hardware complexity. In this paper we propo...
SIGMETRICS
2008
ACM
14 years 9 months ago
2008
ACM
We consider the round robin (RR) scheduling policy where the server processes each job in its buffer for at most a fixed quantum, q, in a round-robin fashion. The processor sharin...
TCAD
2010
14 years 4 months ago
2010
- This paper presents a supervised learning based power management framework for a multi-processor system, where a power manager (PM) learns to predict the system performance state...
ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
ASPLOS
2004
ACM
15 years 3 months ago
2004
ACM
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...