194 search results - page 11 / 39 » Optimizing Technology Mapping for FPGAs Using CAMs |
ICCAD
1995
IEEE
15 years 3 months ago
1995
IEEE
—A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, es...
100
click to vote
DAC
2006
ACM
16 years 20 days ago
2006
ACM
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
FPGA
2008
ACM
15 years 1 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
109
Voted
EDBT
2010
ACM
15 years 6 months ago
2010
ACM
In line with the insight that “one size” of databases will not fit all application needs [19], the database community is currently exploring various alternatives to commodity...
105
click to vote
FCCM
2006
IEEE
15 years 5 months ago
2006
IEEE
FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing r...