194 search results - page 18 / 39 » Optimizing Technology Mapping for FPGAs Using CAMs |
KES
2007
Springer
15 years 6 months ago
2007
Springer
In spatial graphs with a vast number of nodes, it is difficult to compute a solution to graph optimisation problems. We propose an approach using meta-level agents for multi-agents...
FPL
2004
Springer
15 years 5 months ago
2004
Springer
Abstract. Evolvable Hardware (EHW) is a scheme - inspired by natural evolution, for automatic design of hardware systems. By exploring a large design search space, EHW may find so...
BMCBI
2010
14 years 12 months ago
2010
Background: High-throughput sequencing (HTS) technologies play important roles in the life sciences by allowing the rapid parallel sequencing of very large numbers of relatively s...
108
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MICRO
2009
IEEE
15 years 6 months ago
2009
IEEE
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
101
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FPGA
2010
ACM
15 years 8 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...