194 search results - page 25 / 39 » Optimizing Technology Mapping for FPGAs Using CAMs |
RTAS
2007
IEEE
15 years 6 months ago
2007
IEEE
The availability of programmable hardware devices with high density of logic elements and the possibility of implementing CPUs (called softcores) using a fraction of the FPGA area...
108
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IPPS
2003
IEEE
15 years 5 months ago
2003
IEEE
A software framework for the parallel execution of sequential programs using C++ classes is presented. The functional language Concurrent ML is used to implement the underlying ha...
101
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ASPDAC
2005
ACM
15 years 1 months ago
2005
ACM
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
81
Voted
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
Enumeration of bounded size cuts is an important step in several logic synthesis algorithms such as technology mapping and re-writing. The standard algorithm does not scale beyond...
111
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ICRA
2006
IEEE
15 years 5 months ago
2006
IEEE
— The dangerous and time sensitive nature of a disaster area makes it an ideal application for robotic exploration. Our long term goal is to enable humans, software agents, and a...