This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmabilityof FPGAs, or in other wor...
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose pr...
The mapping of image processing algorithms to hardware is complicated by several hardware constraints including limited processing time, limited access to data and limited resourc...
K. T. Gribbon, Donald G. Bailey, Christopher T. Jo...
In this paper, we study the incremental t echnology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-lev...