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ISSS
1997
IEEE
109views Hardware» more  ISSS 1997»
15 years 1 months ago
Reducing the Complexity of ILP Formulations for Synthesis
Integer Linear Programming ILP is commonly used in high level and system level synthesis. It is an NP-Complete problem in general cases. There exists some tools that give an o...
Anne Mignotte, Olivier Peyran
DSD
2002
IEEE
88views Hardware» more  DSD 2002»
15 years 2 months ago
The Synthesis of a Hardware Scheduler for Non-Manifest Loops
This paper1 addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near ...
Omar Mansour, Egbert Molenkamp, Thijs Krol
VLSISP
2008
118views more  VLSISP 2008»
14 years 9 months ago
Analysis of Lifting and B-Spline DWT Implementations for Implantable Neuroprosthetics
Abstract. The large amount of data generated by neuroprosthetic devices requires a high communication bandwidth for extra-cranial transmission, critically limiting the number and u...
Awais M. Kamboh, Andrew Mason, Karim G. Oweiss
DAC
2003
ACM
15 years 10 months ago
Optimal integer delay budgeting on directed acyclic graphs
Delay budget is an excess delay each component of a design can tolerate under a given timing constraint. Delay budgeting has been widely exploited to improve the design quality. W...
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahas...
DATE
2002
IEEE
105views Hardware» more  DATE 2002»
15 years 2 months ago
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
Chunhong Chen, Majid Sarrafzadeh