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MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
14 years 9 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
INFOVIS
1997
IEEE
15 years 1 months ago
H3: laying out large directed graphs in 3D hyperbolic space
We present the H3 layout technique for drawing large directed graphs as node-link diagrams in 3D hyperbolic space. We can lay out much larger structures than can be handled using ...
Tamara Munzner
ITCC
2005
IEEE
15 years 3 months ago
A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks
This paper presents a high performance and scalable elliptic curve processor which is designed to be resistant against timing attacks. The point multiplication algorithm (double-a...
Alireza Hodjat, David Hwang, Ingrid Verbauwhede
ATS
2001
IEEE
137views Hardware» more  ATS 2001»
15 years 1 months ago
Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
Ozgur Sinanoglu, Alex Orailoglu
CODES
2000
IEEE
15 years 2 months ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf