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ISSS
2000
IEEE
15 years 1 months ago
2000
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
ASPDAC
2011
ACM
14 years 1 months ago
2011
ACM
– This paper concerns throughput-constrained parallel execution of synchronous data flow graphs. This paper assumes static mapping and dynamic scheduling of nodes, which has seve...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
— To overcome issues originating from the CMOS technology, a large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits is introduced. LSRDP is ...
ISLPED
1995
ACM
15 years 1 months ago
1995
ACM
ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of ga...
DAC
1998
ACM
15 years 1 months ago
1998
ACM
This paper considers the rate optimal VLSI design of a recursive data flow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We ...