173 search results - page 4 / 35 » Optimizing data flow graphs to minimize hardware implementat... |
167
Voted
AHS
2007
IEEE
15 years 9 months ago
2007
IEEE
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of...
152
Voted
ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
An open architecture tester allows a third party to develop its own instrument. Such a tester must be open in the sense that it needs to be able to integrate this instrument with ...
154
Voted
CODES
2004
IEEE
15 years 9 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
159
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FCCM
2006
IEEE
15 years 11 months ago
2006
IEEE
Field-Programmable Gate Arrays (FPGAs) are being employed in high performance computing systems owing to their potential to accelerate a wide variety of long-running routines. Par...
176
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VIS
2004
IEEE
16 years 6 months ago
2004
IEEE
Feature detection in flow fields is a well researched area, but practical application is often difficult due to the numerical complexity of the algorithms preventing interactive u...