173 search results - page 5 / 35 » Optimizing data flow graphs to minimize hardware implementat... |
ICCAD
2000
IEEE
15 years 2 months ago
2000
IEEE
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
ISSS
1999
IEEE
15 years 1 months ago
1999
IEEE
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
WSCG
2003
14 years 11 months ago
2003
We present a method for real-time level of detail reduction that is able to display high-complexity polygonal surface data. A compact and efficient regular grid representation is...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
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ISCAS
1999
IEEE
15 years 1 months ago
1999
IEEE
In this paper, we present the application of dynamic trellis diagrams (DTDs) to automatic translation of data flow graphs (DFGs) into highly optimized programs for digital signal ...