We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Vale...
Abstract In many problems from different disciplines such as engineering, physics, medicine, and biology, a series of experimental data is used in order to generate a model that ca...
Georges K. Saharidis, Ioannis P. Androulakis, Mari...
Detecting symmetries has many applications in logic synthesis that include, amongst other things, technology mapping, deciding equivalence of Boolean functions when the input corre...
Transformations using retiming and resynthesis operations are the most important and practical (if not the only) techniques used in optimizing synchronous hardware systems. Althoug...