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» Optimizing for parallelism and data locality
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114
Voted
ASAP
2007
IEEE
136views Hardware» more  ASAP 2007»
15 years 11 months ago
0/1 Knapsack on Hardware: A Complete Solution
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
K. Nibbelink, S. Rajopadhye, R. McConnell
GBRPR
2007
Springer
15 years 11 months ago
Hierarchy Construction Schemes Within the Scale Set Framework
Segmentation algorithms based on an energy minimisation framework often depend on a scale parameter which balances a fit to data and a regularising term. Irregular pyramids are de...
Jean-Hugues Pruvot, Luc Brun
122
Voted
IPPS
2006
IEEE
15 years 11 months ago
Chedar: peer-to-peer middleware
In this paper we present a new peer-to-peer (P2P) middleware called CHEap Distributed ARchitecture (Chedar). Chedar is totally decentralized and can be used as a basis for P2P app...
Annemari Auvinen, Mikko Vapa, Matthieu Weber, Niko...
173
Voted
HOTI
2005
IEEE
15 years 11 months ago
SIFT: Snort Intrusion Filter for TCP
Intrusion rule processing in reconfigurable hardware enables intrusion detection and prevention services to run at multi Gigabit/second rates. High-level intrusion rules mapped d...
Michael Attig, John W. Lockwood
IPPS
2005
IEEE
15 years 11 months ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna