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» Optimizing for parallelism and data locality
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DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
15 years 4 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
CCGRID
2006
IEEE
15 years 4 months ago
Proposal of MPI Operation Level Checkpoint/Rollback and One Implementation
With the increasing number of processors in modern HPC(High Performance Computing) systems, there are two emergent problems to solve. One is scalability, the other is fault tolera...
Yuan Tang, Graham E. Fagg, Jack Dongarra
CONCUR
2005
Springer
15 years 3 months ago
Concurrent Clustered Programming
d Abstract) Vijay Saraswat1 and Radha Jagadeesan2 1 IBM T.J. Watson Research Lab 2 School of CTI, DePaul University Abstract. We present the concurrency and distribution primitives...
Vijay A. Saraswat, Radha Jagadeesan
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
15 years 3 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
ICS
2005
Tsinghua U.
15 years 3 months ago
The implications of working set analysis on supercomputing memory hierarchy design
Supercomputer architects strive to maximize the performance of scientific applications. Unfortunately, the large, unwieldy nature of most scientific applications has lead to the...
Richard C. Murphy, Arun Rodrigues, Peter M. Kogge,...