1912 search results - page 149 / 383 » Optimizing interconnection policies |
158
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CODES
2007
IEEE
15 years 12 months ago
2007
IEEE
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
149
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ASPDAC
2006
ACM
15 years 11 months ago
2006
ACM
— Buffer insertion is an effective technique to reduce interconnect delay. In this paper, we give a simple O(mn) time algorithm for optimal buffer insertion, where m is the numbe...
172
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IPPS
2005
IEEE
15 years 11 months ago
2005
IEEE
Mobile Ad-hoc Networks (MANETs) are composed of a set of communicating devices which are able to spontaneously interconnect without any pre-existing infrastructure. In such scenar...
160
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ICS
2005
Tsinghua U.
15 years 11 months ago
2005
Tsinghua U.
BlueGene/L is currently the world’s fastest supercomputer. It consists of a large number of low power dual-processor compute nodes interconnected by high speed torus and collect...
153
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ASPDAC
2004
ACM
15 years 11 months ago
2004
ACM
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...