2703 search results - page 122 / 541 » Optimizing memory transactions |
123
Voted
ICCD
2001
IEEE
16 years 11 days ago
2001
IEEE
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
144
Voted
SIGMOD
2011
ACM
14 years 6 months ago
2011
ACM
In this demonstration we present BRRL, a library for making distributed main-memory applications fault tolerant. BRRL is optimized for cloud applications with frequent points of c...
142
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HPCA
2002
IEEE
15 years 8 months ago
2002
IEEE
Configurations of contemporary DRAM memory systems become increasingly complex. A recent study [5] shows that application performance is highly sensitive to choices of configura...
138
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CF
2009
ACM
15 years 10 months ago
2009
ACM
Hybrid architectures combining the strengths of generalpurpose processors with application-specific hardware accelerators can lead to a significant performance improvement. Our ...
120
Voted
PDP
2006
IEEE
15 years 9 months ago
2006
IEEE
Commodity symmetric multiprocessors (SMPs), though originally intended for transaction processing, because of their availability, are now used for numerical analysis applications ...