2703 search results - page 213 / 541 » Optimizing memory transactions |
149
Voted
IPPS
2006
IEEE
15 years 9 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
129
Voted
ASPDAC
2004
ACM
15 years 9 months ago
2004
ACM
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
136
Voted
ICS
2010
Tsinghua U.
15 years 8 months ago
2010
Tsinghua U.
We explore the intersection between an emerging class of architectures and a prominent workload: GPGPUs (General-Purpose Graphics Processing Units) and regular expression matching...
154
Voted
EH
2004
IEEE
15 years 7 months ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
128
Voted
JCP
2008
15 years 3 months ago
2008
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...