2703 search results - page 220 / 541 » Optimizing memory transactions |
132
Voted
SIROCCO
2008
15 years 5 months ago
2008
In the effort to understand the algorithmic limitations of computing by a swarm of robots, the research has focused on the minimal capabilities that allow a problem to be solved. ...
169
Voted
ISCAPDCS
2004
15 years 5 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
260
Voted
POPL
2006
ACM
16 years 4 months ago
2006
ACM
The movement to multi-core processors increases the need for simpler, more robust parallel programming models. Atomic sections have been widely recognized for their ease of use. T...
116
Voted
ASPLOS
2010
ACM
15 years 10 months ago
2010
ACM
This paper introduces a new abstraction to accelerate the readbarriers and write-barriers used by language runtime systems. We exploit the fact that, dynamically, many barrier exe...
181
Voted
SIGMOD
2011
ACM
14 years 6 months ago
2011
ACM
Advances in hardware have enabled many long-running applications to execute entirely in main memory. As a result, these applications have increasingly turned to database technique...